![]() China turns to older DUV technology for 3nm chipsRead the article English (automatic translation) |
SummaryResearchers at the Chinese Academy of Sciences demonstrated an early-stage process for producing gate-all-around (GAA) transistors at sub-3 nm levels using DUV lithography. This work offers a potential alternative to China's blocked access to ASML's EUV machines. Based on statements from a single experienced researcher via Digitimes, the study is explicitly in a pre-production stage and has not been validated at the wafer scale. |
Why it mattersIf China can achieve sub-3 nm performance using DUV tools, it would weaken the strategic impact of EUV export restrictions that underpin US and Dutch semiconductor policy. Even at the research stage, this signal is significant: it shows Chinese labs are matching new transistor architectures (GAA) with older lithography technologies to close the node gap. This adds to a portfolio of parallel alternative solutions, including Huawei's 'Tau Scaling Law' design approach. |
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Critical takeThe article relies on statements from a single researcher relayed via Digitimes; there are no peer-reviewed papers, yield data, or references to independent reproducibility. Describing this work as a 'path to advanced chip manufacturing' risks turning laboratory curiosity into a near-term competitive threat. The warning that the process is 'early-stage' and 'not ready for production' is lost beneath headlines framing it as a meaningful alternative. This framing serves geopolitical narrative more than engineering reality. |
