No. 63
2026-09-20
the AI pulse — brewed, not raw
 AI CRITIQUE
Parlak bir şekilde aydınlatılmış bir bilgisayar çipi, karmaşık bir devre kartının üzerinde durmakta olup etrafı kırmızı parlayan vurgulara sahip daha küçük elektronik bileşenlerle çevrilidir.

China turns to older DUV technology for 3nm chips

Read the article    English (automatic translation)

Summary

Researchers at the Chinese Academy of Sciences demonstrated an early-stage process for producing gate-all-around (GAA) transistors at sub-3 nm levels using DUV lithography. This work offers a potential alternative to China's blocked access to ASML's EUV machines. Based on statements from a single experienced researcher via Digitimes, the study is explicitly in a pre-production stage and has not been validated at the wafer scale.

Why it matters

If China can achieve sub-3 nm performance using DUV tools, it would weaken the strategic impact of EUV export restrictions that underpin US and Dutch semiconductor policy. Even at the research stage, this signal is significant: it shows Chinese labs are matching new transistor architectures (GAA) with older lithography technologies to close the node gap. This adds to a portfolio of parallel alternative solutions, including Huawei's 'Tau Scaling Law' design approach.

Highlights

  • The GAA-on-DUV work is explicitly early-stage; no wafer-level validation or commercial-scale demonstration has been provided.
  • Samsung is already using 3 nm GAA in mass production, and TSMC is transitioning to GAA at 2 nm in 2025. The architectural target is well understood; however, the DUV process path remains an unproven variable.
  • Huawei's 2026 'Tau Scaling Law' (time-scaling design) is a separate design-level strategy claiming 1.4 nm-equivalent density by 2031; it is not a lithography breakthrough.

Critical take

The article relies on statements from a single researcher relayed via Digitimes; there are no peer-reviewed papers, yield data, or references to independent reproducibility. Describing this work as a 'path to advanced chip manufacturing' risks turning laboratory curiosity into a near-term competitive threat. The warning that the process is 'early-stage' and 'not ready for production' is lost beneath headlines framing it as a meaningful alternative. This framing serves geopolitical narrative more than engineering reality.

Bu kritik, yerel yapay zeka modeli Qwen3.8-27B tarafından yazılmıştır. Haberi ben seçtim; kritik metnini yayımlanmadan önce tek tek denetlemiyorum.This critique was written by the local AI model Qwen3.8-27B. I chose the story; I do not review each critique before it is published.
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