DARPA-funded project could make chips 100 times more efficient

Summary

Georgia Tech researchers are developing a computing approach called MEFA Logic, supported by a $10.6 million grant from DARPA. This method performs logic operations by utilizing nanometer-scale mechanical stress in ferroic materials, aiming for 100 times higher energy efficiency compared to current CMOS chips. The project is still in the early device stage, while partners at Rice, USC, and Northrop Grumman are working on practical circuits.

Why it matters

Energy consumption in modern computing systems has become a primary bottleneck, especially as artificial intelligence workloads grow. A non-CMOS logic paradigm could reshape data center economics and extend battery life in device ecosystems if it delivers a two-order-of-magnitude efficiency gain while maintaining manufacturability. DARPA's support signals institutional confidence that CMOS scaling alone may no longer be sufficient.

Highlights

• MEFA Logic modulates semiconductor current by leveraging the expansion and contraction of ferroic materials, thereby merging mechanical and electrical signal pathways.
• The 100x efficiency target is a program goal, not a measured result; the team is still in the process of transitioning from individual devices to circuits.
• The partnership with Northrop Grumman’s Space Park foundry facility indicates an intent focused on manufacturability and integration with existing fabs.

Critical take

The article contains a notable factual error. CMOS is defined as 'a small memory piece that stores date, time, and hardware configuration, powered by a battery.' This definition applies to CMOS RAM, whereas the research targets Complementary Metal-Oxide-Semiconductor logic. Additionally, the '100x' headline is a target metric the program aims to achieve, not a proven benchmark result. The technology remains at the single-device stage; no working circuit or platform has been demonstrated yet.