How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip

Summary

OpenAI designed the Jalapeño AI accelerator, announced in August 2026, in less than 20 months. This process utilized large language model (LLM)-assisted workflows and involved a team of approximately 100 people. Physical design was carried out by Broadcom. The chip claims 13.4 petaflops performance in 4-bit operations, 232 GB of HBM4 memory, and up to 3.6x lower latency compared to the Nvidia GB300.

Why it matters

This is a concrete, high-profile example of large language models moving beyond lab demos and being integrated into a real silicon design pipeline. It signals that AI-assisted chip design has transitioned from the promise stage to the production stage. As models improve and timelines tighten further, cost and speed barriers for custom silicon could drop sharply. This could reshape the competitive dynamics between hyperscale providers and traditional fabless chipmakers.

Highlights

• The time from RTL to tapeout was only about 9 months. Excluding Broadcom, a team of fewer than 100 people on average worked on it.
• Large language models were applied to the 'linguistic domain' of the design via Google's XLS high-level synthesis chain (DSLX/C++ → Verilog).
• Independent experts (Verkor.io, UC San Diego) found the timeline credible. However, they emphasized that Broadcom's role in physical design was indispensable.

Critical take

The article relies heavily on OpenAI's own benchmarks and the statements of a single vice president. The most critical caveat—that Broadcom handled gate-level physical design—is buried in the middle of the text. Skeptics argue that this role is the reason the timeline was found 'credible' rather than 'extraordinary.' The article also fails to clarify how much of the LLM-assisted workflow was original versus reused open-source tools. This makes the headline 'AI designed the chip' somewhat exaggerated.