Silicon chip reaches 200 Gb/s speed with slow light technology

Summary

Japanese researchers at Yokohama National University have introduced a 320-micron silicon photonic crystal modulator that achieves 200 Gb/s speeds by combining slow-light enhancement with an integrated electro-optic equalizer. This design targets high-density optical interconnects in AI data centers.

Why it matters

AI data centers are hitting electrical interconnect bandwidth limits. Reducing the optical modulator's footprint from millimeters to sub-millimeters while maintaining CMOS compatibility could significantly increase port density per chip package. If insertion loss and multi-channel issues are resolved, this architecture could form the basis for co-packaged optics, substantially reducing energy and area costs at scale.

Highlights

• Device length: 320 µm (compared to 2–4 mm in traditional Mach-Zehnder modulators); total area ≈ 0.4 mm²
• Bandwidth was boosted to 35→80 GHz in one design and 23→55 GHz in another, thanks to the integrated EO equalizer
• 200 Gb/s at 63 fJ/bit with PAM-4 and an 11-tap receiver equalizer; 140 Gb/s OOK at just 26 fJ/bit

Critical take

The headline 200 Gb/s figure relies on an 11-tap equalizer on the receiver side. Therefore, the result represents a system-level achievement rather than pure modulator capability. The 11.7–15.5 dB insertion loss, which is compensated by an optical amplifier in the lab, remains a significant practical hurdle. The 3.2–6.4 Tbps multi-channel estimate is explicitly a design projection, not a measured value. Consequently, the path from this proof-of-concept to a deployable co-packaged optics product is still several engineering iterations away.