Quantinuum Demonstrates 99.9995% Logical Memory Fidelity on Helios

Summary

Quantinuum reported 99.9995% logical memory fidelity (5×10⁻⁶ error rate) on its Helios ion trap processor using distance-7 triangular color codes. A suppression factor of Λ=12 was recorded for code distances of 3, 5, and 7. The company also demonstrated neural network decoders with sub-millisecond latency and projected that approximately 30,000 physical qubits could yield 100 logical qubits at error rates of 10⁻¹².

Why it matters

Demonstrating exponential error suppression below the color code threshold on a commercial ion trap platform is a concrete step toward fault-tolerant quantum computing, moving the field beyond the proof-of-concept stage. Sub-millisecond decoder latencies on commercial GPUs (H100) address one of the practical bottlenecks for real-time quantum error correction. These results are explicitly benchmarked against Quantinuum’s 2029 Apollo target, providing investors and researchers with a measurable roadmap.

Highlights

• 99.9995% logical memory fidelity at distance-7, although the logical 2-qubit Clifford gate error remains at 7×10⁻⁵, which is one order of magnitude worse than the memory fidelity.
• 3D CNN and Round-Token Transformer decoders achieved 0.2–0.5 ms per round on NVIDIA H100s without requiring hardware-specific fine-tuning.
• Quantinuum projects that approximately 30,000 physical qubits will be needed for 100 logical qubits at 10⁻¹² error rates, assuming the Λ=12 scaling is maintained.

Critical take

The fidelity value cited in the headline refers to memory performance at a single code distance. The metric that truly determines the feasibility of fault-tolerant algorithms is the gate-level result (7×10⁻⁵ for transversal CNOT), which is two orders of magnitude higher than the memory value. Furthermore, the 30,000-qubit projection is an extrapolation derived from a three-point fit (d=3, 5, 7) in a corporate preprint, not a peer-reviewed demonstration. Consequently, the scaling claim should be treated as a target rather than a validated engineering constraint.