Siemens speeds up chip design with Solido Layout Analyzer

Summary

Siemens introduced the Solido Layout Analyzer at DAC 2026. This post-layout analysis tool, integrated within the Solido Design Environment, directly links extracted parasitics and layout-dependent effects to circuit performance specifications using a sensitivity-based approach in the simulation loop. The tool supports Fuse, an 'agentic' interface that operates in natural language.

Why it matters

As transistor counts increase and layout/routing effects become increasingly dominant over device parameters in advanced nodes, late-stage parasitic cleanup can take weeks in the production cycle. A tool that automates root cause identification and scenario experimentation can shorten this bottleneck. However, the tool's true value depends on whether it performs better than existing sign-off flows, rather than merely repackaging them.

Highlights

• Four structured workflows (Discover Parasitics, Discover LDE, Output Impacts, Experiments) cover the entire post-layout cleanup cycle, from outlier detection to directed ECO decisions.
• The 'measurement-aware' framework links extracted DSPF data to test benches and performance specifications, moving beyond the visualization-only approach of traditional tools.
• The natural language agent layer (Fuse) handles file processing, job execution, and report generation, reducing the manual burden surrounding core analysis.

Critical take

This is a vendor marketing piece that offers no zero-baseline benchmarks or head-to-head comparisons with existing sign-off tools. It also suspiciously vaguely defines what 'AI-assisted' means beyond a chat-style wrapper (Fuse) layered on top of sensitivity analysis and scenario simulation workflows. Until independent users publish cycle time or yield data, the 'weeks saved' claim remains an unverified promise dressed up in agentic jargon.